The invention relates to a method for arranging chips of a first substrate on a second substrate.
List of Reference Symbols
    100 300 mm silicon wafer    101 Chip groups    102 First chips    103 Second chips    104 Third chips    105 Fourth chips    106 Fifth chips    107 Sixth chips    108 Seventh chips    109 Eighth chips    110 Ninth chips    111 200 mm silicon wafer    112 Mapping    113 Sawing lines    114 Grid    200 Cross-sectional view    201 Adhesive
The current development in semiconductor technology is being concentrated increasingly on the processing of silicon wafers having a diameter of 300 mm. For cost reasons, developements in this technology generation are increasingly being carried out in development cooperations between a plurality of development partners.
In view of the rising quality requirements made of semiconductor products, it is necessary to monitor the functionality of a semiconductor product during and after a production process. For this purpose, test structures may be provided on a wafer, which usually has a multiplicity of electronic chips, a production process for forming integrated semiconductor circuits being monitored by means of said test structures. The extent or the number of available test structures increases as the wafer area increases, so that, in the transition from the 200 mm technology generation to the 300 mm technology generation, the number of test structures required for ensuring a good quality of semiconductor products produced also rises, to be precise in particular at least proportionally to the wafer area. Such PCM measurements (process control monitoring) involve checking, for example, whether the threshold voltage of transistors formed has an acceptable value, whether the nonreactive resistance of interconnects formed has an acceptable value, etc.
The high costs of a wafer require a comprehensive evaluation which, in the case of electrical measurements at the wafer level, can essentially only be effected sequentially, i.e. one after the other. The measurement time required for evaluating or monitoring the quality of a wafer likewise rises with the number of test structures.
In a development alliance of a plurality of semiconductor development partners for jointly developing a semiconductor product, the individual development partners in each case contribute their own blocks of test structures, which are often evaluated by development partner-specific employees in development partner-specific laboratories. On a wafer allocated to one development partner, the test structures of the other development partners often remain largely unused. At the very least the further utilization by other development partners is delayed.
The simultaneous utilization of different sub-chips of a wafer or of different test structures is possible if the structures are sawn and subsequently incorporated into individual housings in order subsequently to be examined there. This procedure is usually used for long-term examinations.
However, only a limited number of contacts can be bonded in this procedure. A subsequent alteration is not possible. Moreover, the configuration of such contacts has to be defined at an early point in time. The sequential examination of very many test structures is very complicated since housing costs and processing costs have to be taken into account for each test structure. In addition, considerable area on the wafer is lost due to a correspondingly large number of sawing lines.
To put it another way, when a chip with test structures is incorporated into a housing, it is necessary to define, as early as upon incorporation, which of the chip contacts (or which small number of chip contacts from a substantially larger number of possible chip contacts) of the chip in the housing is intended to be externally contact-connectable. As a result, the chip contacts that can be examined later are highly circumscribed in an undesirable manner at a point in time at which it is often not yet foreseeable what circumscription of contacts to be contact-connected is expedient.
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